The purpose of this lab is to see how hazard detection works in the pipelined datapath and to trace instructions through the pipelined datapath.
To see how hazard detection works in the pipelined datapath, consider the following code as it passes through the datapath in Figure 6.36:
Address Instruction ======= ================= 4000 add $s0, $s0, $s2 4004 add $t3, $t3, $s3 4008 lw $t0, -4($s0) 4012 add $t0, $t0, $t3 4016 sw $t0, -4($s0)Assume the register file contains the following values BEFORE the first instruction executes:
Register Value ======== ===== s0 80000 s2 4 s3 1 t3 0Also assume data memory contains the following values before the first instruction executes:
Address Value ======= ===== 79992 15 79996 16 80000 17 80004 18 80008 19First, draw a diagram similar to Figure 6.35 that shows how these instructions would be pipelined, including the stall for the dependency between lw and add $t0. Be sure to leave the original IF and ID stages for add $t0 in the diagram before the stall occurs (as shown in Figure 6.35 for the and instruction). This will make it easier to answer the following questions.
Number the cycles on your diagram, beginning with cycle 1 for the IF stage
of add $s0, $s0, $s2. The hazard detection for the load word
instruction will occur in cycle 5 of the pipeline (the EX stage of load word
and the original ID stage of add $t0 before the stall).
Answer the following questions. If the storage register will contain data read from memory or the register file, refer to the above tables for their current values: