Homework 4 - Chapters 5 and 6

Due: Friday, February 20, 2009 at 5:00pm
NOTE: Late assignments will only be accepted until 5:00pm on Sunday, February 22, 2009.
At that point, the solution will be posted so that you may study it for Midterm 2. No late assignments will be accepted after the solution has been posted.

  1. (2 pts) With regards to exception handling, how is the cause of the exception and the instruction that caused the exception represented in MIPS?
  2. (4 pts) How are the following exceptions detected in the multicycle datapath, as described in section 5.6?
    1. Integer overflow
    2. Undefined instruction
  3. (4 pts) How would you extend the state diagram for control in the multicycle datapath to detect the following exceptions?
    1. Divide by zero
    2. Invalid data memory address
  4. (2 pts) What is the motivation behind using a pipelined datapath as opposed to a simple or multicycle datapath?
  5. (2 pts) What is a data hazard in the pipelined datapath? How can it be handled?
  6. (2 pts) What is a control hazard in the pipelined datapath? How can it be handled?
  7. (4 pts) In the following MIPS assembly code, identify all the hazards that are present. Show how to reorder the instructions to minimize the number of stalls due to data hazards.
        Loop: beq  $t5, $a1, Exit      # if t5 == a1, exit loop
              lw   $t0, 0($a0)         # Load fib(n-2)
              lw   $t1, 4($a0)         # Load fib(n-1)
              add  $t2, $t0, $t1       # Calculate fib(n)
              sw   $t2, 8($a0)         # Store fib(n)
              add  $a0, $a0, $s1       # s1 contains 4
              add  $t5, $t5, $s2       # s1 contains 1
              j    Loop
        Exit: