Dr. Melissa Danforth

Computer and Electrical Engineering and Computer Science Department
California State University, Bakersfield

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CMPS 321 Computer Architecture - Sections 1 and 2 - Winter 2013
Course meets MWF 3:30 - 4:40pm and Tu 3:15 - 5:45pm in Sci III 315
Course Description
This course follows the Digital Logic Design course and focuses on the design of the CPU and computer system at the architectural (or functional) level: CPU instruction sets and functional units, data types, control unit design, interrupt handling and DMA, I/O support, memory hierarchy, virtual memory, and buses and bus timing. In contrast, the Digital Logic Design course is primarily concerned with implementation; that is, the combinatorial and sequential circuits which are the building blocks of the functional units.
CMPS 223
ACM/IEEE Body of Knowledge Topics:
CC-AR4: Memory system organization and architecture
CC-AR5: Interfacing and communication
CC-AR6: Functional organization
CC-AR7: Multiprocessing and alternative architectures
Computer Organization and Design, 4th edition (revised printing). David A. Patterson and John L. Hennessy. Publisher: Morgan Kaufmann Publishers, 2012. ISBN: 978-0-12-374750-1
Moodle Link
The direct link to the course on Moodle is http://moodle.cs.csubak.edu/moodle/course/view.php?id=66