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Catalog Description :
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This course follows the Digital Logic Design course
and focuses on the design of the CPU and computer system at the
architectural (or functional) level:
CPU instruction sets and functional units, data types, control unit
design, interrupt handling and DMA, I/O support, memory hierarchy,
virtual memory, and buses and bus timing. In contrast, the Digital
Logic Design course is primarily concerned with implementation:
that is, the combinatorial and sequential circuits which are the
building blocks of the functional units.
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Prerequisite:
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CMPS 223 and CMPS 320
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Units:
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5
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Coordinator:
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Marc Thomas
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Goals/Objectives:
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- Understand the design tradeoffs involved
in computer architecture (e.g. performance vs.
flexibility).
- Understand how poor programming can result
in very inefficient use of the hardware.
- (Laboratory) Become proficient in writing,
profiling, and analyzing programs which need to make
intensive use of one or more of the following architectural
features: the CPU, virtual memory, and I/O devices.
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Current Texts:
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- William Stallings, Computer Organization
and Architecture (6th edition) ,
ISBN 0-13-035119-9
- (historical) John Hayes, Computer
Architecure and Organization
- (historical) Levy and Eckhouse, Computer
Programming and Architecture: the VAX-11
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Topics:
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- Introduction to digital systems: What constitutes
a general purpose computer; design of a minimal hardwired CPU.
Historical development of computing and some case
studies: the first, second, and third generations: design of
a minimal microcoded CPU.
- (AR3) Assembly level machine organization: System buses, timing, arbitration, and bus
protocol; the general fetch-execute cycle with interrupts;
multiple bus systems.
- (AR4) Memory system organization & architecture: Memory design and hierachy; alignment;
L1 and L2 caches; paging and virtual memory; the TLB cache;
memory error detection and correction; relative access times.
- (AR5) Interfacing, communication External storage devices: magnetic and optical.
buffering of I/O, polling, interrupt-driven I/O, interrupt-driven I/O with DMA.
- Operating system support and interface to the
hardware: system calls and device drivers; multiplexing I/O.
- (AR6) Functional organization: integer and floating-point units,
CPU instruction sets and addressing modes, RISC;
CISC, long instruction word RISC processors (e.g. Itanium), benchmarks,use of multiple functional units, pipelining..
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ACM Sub Areas or Units Covered::
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ACM Sub Areas or Units covered in this course:
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(AR1) Digital logic and digital systems (covered in prerequisite CMPS 320)
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0.0
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(AR2) Machine level representation of data (covered in prerequisite CMPS 320)
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0.0
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(AR3) Assembly level machine organization
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X.Y
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(AR4) Memory system organization and architecture
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X.Y
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(AR5) Interfacing and communication
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X.Y
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(AR6) Functional organization
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X.Y
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AR: Architecture and Organization
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Laboratory:
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The laboratory session will parallel the lecture,
illustrating the principles. We will often write programs which
simulate various features of and considerations in computer
architecture. I will provide a library of timing routines
for profiling programs.
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Oral and Written Communication:
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Social and Ethical Issues:
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Problem Analysis:
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Solution Design:
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Version & Date
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Version 1, 5/6/2003
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Comments
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The first draft based on ACM curricula 2001 in the format of
ABET sample course description.
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